Cadence Tutorial 4

The following Cadence CAD tools will be used in this lab:

Virtuoso Composer(formerly a.k.a. Composer) for schematic capture.
Analog Environment (formerly a.k.a. Analog Artist) for simulation.

In order to setup your environment to run Cadence applications you need to open an xterm window and type (EVERY TIME you login and in each window you want to run a Cadence tool)

. cadence

this script modifies your environment (sets PATH and exports variables).

If you have problems with your CLASS account please send email to eeadmin@virginia.edu

If you have problems using one of the Cadence applications please see your TA.

Running the Cadence tools

Please go to your cadence directory and start icfb:

cd cadence icfb &

The command icfb & starts Cadence in the background. For more information on the various Cadence tools I encourage you to read the corresponding user manuals. You can open the on-line manuals by typing:

openbook &

You can also get to the manuals by pressing the Help button on any Cadence window (e.g. CIW). Spend some time browsing the manuals to understand what is available. During the semester you will have to look for information in the on-line manuals to complement the (limited) info given by the tutorials.

Now start the Library Manager by going to Tools -> Library Manager on the Tools menu of the CIW. The lab1 library that you created previously should still appear in the Library Manager window. You can still use the same library for now. In this lab we are going to learn some more skills in using the Cadence tools. Let's start our fourth schematic now!

PASSING PARAMETERS ACROSS HIERARCHY

In this Lab 4 we are going to create a hierarchical schematic at the logic (gate) level by using symbols for lower level schematics. When creating such a schematic it is sometimes necessary to use different gates with the same logic but with different transistor sizes (e.g. a "weak" inverter and a "strong" inverter). Also sometimes it is good to be able to easily move from one technology to another (e.g. from 0.35u to 0.25u) without a lot of effort. For these purposes it is better if the sizes of the transistors are parameterized twice:

one set of parameters for passing the transistor sizes across hierarchy such that we can use the same gate schematic and symbol for different "strengths",
another set of parameters that can globally change the sizes for all transistors in the schematic.

In this section we will learn to use both of these methods. We will use the schematic and symbol for the inverter that we created in Tutorials 2 and 3 (you may want to go back and refresh your memory). Open the schematic view of the inverter by double clicking on the schematic view in the Library Manager window. We now need to change the properties Width and Length for the transistors such that they are parameterized. Edit properties for the nmos and change Length to: [@L:%:0.35u] (type exactly like this) and Width to: [@Wn:%:1u], then pmos and change Length to: [@L:%:0.35u] and Width to: [@Wp:%:1.5u].

parprop

Check and save your design and make sure you get no errors. By doing this we have created parameterized transistor sizes where both the pmos and nmos have the same length with parameter L and default value 0.35u, while the widths are parameters Wp and Wn with default values 1.5u and 1u. When we use this inverter in a hierarchical schematic we can now keep the default values (by doing nothing) or change the default values to go to a different technology (e.g. change L to 0.25u) or have different transistor strengths for different inverters.

Let's do that by creating a new schematic, call it InvDelay. Close the inverter schematic and go to the Library Manager. Now we can create a hierarchical schematic that uses the inverter symbols. Go to the Library Manager and with the lab1 library highlighted do File -> New -> Cell View and create a schematic view for a cell named InvDelay. The Composer schematic editor window should open up. Let's create a schematic of 4 cascaded inverters with an input port IN and an output port OUT after the third inverter. You may need to go to the previous labs if you don't remember all the steps.

schinvdel

Do Check and Save. You should get one warning about the output of the last inverter which is floating. Let's get rid of that warning by placing an instance of the noConn instance from the basic library on that output.

noconn

Also add labels to the internal nets by doing Add -> Wire Name, filling the names: INPUT1 INPUT2 in the dialogue box and then click on the two nets, then on CANCEL.

addname

Now when you do a Check and Save you should get no errors or warnings and the two internal nets should have names.

schnowar

Now let's assign different sizes to the 4 inverters. Let's assume that we are interested in the inverter delay for a fanout of 2, this means that we could use identical inverters and place 1 more of them at each output (we did that in Lab 3). This time let's use a different method by using different size inverters and assume that an inverter 2 times larger than the base size is equivalent to 2 base inverters (if you are unclear about this please come and see me). This means that we can keep the first inverter at the base size, make the second one 2 times larger, the 3rd one 4 times larger and the 4th one 8 times larger. We can do this now since we have already defined the parameterized transistor sizes for the inverter Wn, Wp and L. Go to Edit -> Properties -> Objects and then click on the first inverter. We need to define the 3 new properties (Wn, Wp, L) at the symbol level. You do this by clicking Add in the Edit Object Properties dialogue box and then filling the name (one of Wn, Wp, L) and then the Value. We'll keep the Value as a global parameter so we can keep the Type as string. Fill Wn as 1u and Wp as a*1u for the first inverter, Wn as 2u and Wp as a*2u for the second inverter, Wn as 4u and Wp as a*4u for the third inverter and Wn as 8u and Wp as a*8u for the last inverter, where a is a parameter for the pmos to nmos ratio. Also turn on the Display to value. Notice that we left the Length parameter L to its default value (0.35u). An example of the Add Property dialogue box for Wp for the first inverter:

addprop

And the resulting Edit Object Properties for the first inverter:

editprop

We also need to add vdd! and gnd! symbols from the to the top schematic. Check and Save your schematic, it should look like this:

schfanout

The last skill in the schematic entry for now will be to traverse hierarchy. For this go to Design -> Hierarchy -> Descend Edit and then click on the first inverter and then clik OK. You should get to the inverter schematic where you can verify that the sizes are actually changed according to the setting at the higher level (e.g. W for pmos is = a*1u).

downhier

In principle now you could edit this schematic if necessary but for now go back to Design -> Hierarchy -> Return.

SIMULATION

We made the previous schematic for determining the optimum pmos to nmos ratio (a) for a fanout of 2 through simulation. The two inverters that make the actual circuit used for delay are the second and third. The first inverter is used only to make the rise and fall times more realistic (better than a simple step or piecewise linear) and the last inverter is used only as load. We use two inverters for delay such that we take both tpLH and tpHL into account without having to do manual addition. First let's make sure the inverters work. In the Composer window go to Tools -> Analog Environment (the name has changed!). The design should be set to the right Library, Cell and View. Go to Setup -> Model Libraries and choose (you can type directly or use Browse)
/net/eeuva.us1/mrs8n/cadence/models/c10spectre.mod then click Add, then OK. If you have an old state that you saved you can also load that state to save on typing. We also need to set up inputs and power supply since we don't have explicit voltage sources. Go to Setup -> Stimuli. We need to setup both inputs (IN) and the global sources (power supply). For IN use a pulse 2.5 amplitude with 0.1n rise and fall times and 0.4n pulse width and 1n period, make sure you enable it. Click on the Global Sources, you should have only one (vdd!). Click on Enabled, Function dc, Type Voltage, DC voltage 2.5, Source type dc, and click on Apply. The vdd! should turn from OFF to ON. You may want to revisit Lab 2 if you have trouble with this. CAUTION Cadence is very fragile concerning this dialog box, make sure you enter the numbers exactly as above (i.e. no space between the digit and n, etc.). If you get syntax errors later in siumlation they are most likely because of this. Now you need to choose the type of simulation, go to Analyses -> Choose... In this case we will choose tran which is the default, 2n as the Stop time and moderate as the accuracy default. Now go to Outputs -> Save All and make sure allpub is checked for signals to save (default). Click OK. CAUTION In general, once you have a big schematic, you will want to only save a few signals for simulation, this will make your simulation faster. For small circuits as we have now it doesn't make a big difference though.

The only other setting that we need is the variable a, for now let's set it to 2 (the rule of thumb), go to Variables -> Edit and then in the dialogue box enter a as Name and 2 as value.

editvar

The variable a should now appear in the Design Variables list:

simenv

Now we can finally simulate! Click on the Netlist and Run button (looks like a green light) on the right or go to Simulation -> Netlist and Run. Click OK on the Welcome to Spectre window which should start the simulation. In case you have errors you will need to go back and correct them. This can be tricky! You may need to do Simulation -> Netlist -> Recreate if you change the schematic. CAUTION Each time you change the schematic you have to do Check and Save!. Assuming there are no errors you can now admire the simulation results. Go to Results -> Direct Plot -> Transient Signal which will pop-up your schematic window. Now you have to click on the signals you want to see. Since this is a transient analysis we want to see a few voltages. In order to do this you have to click on the desired nets, then the ESC key. Click on OUT, INPUT1 and INPUT2.

wavemeas

Now we can measure tpLH, tpHL for the second and third inverters. To do this accurately we are going to use the waveform calculator. Go to Tools -> Calculator in the Analog Environment window which should pop up the calculator. Get familiarized with the calculator, you may also want to consult Openbook. The calculator works with a "stack" in which you first input a waveform or more and then you perform an operation. After each operation it's recommended that you clear the stack (clst). To view the stack you have to enable it (click on the button Display Stack). Now click on wave in the calculator window and then click on the INPUT2 wave in the waveform window. A wave should be displayed in the calculator. Now press on the INPUT1 wave which should push the first wave in the stack and bring this new wave in the calculator. IMPORTANT: Note that we entered the waves in reverse order (the late first, then the early one), this is a "feature" of the stack operation of the calculator.

calc

Now go to Special Functions in the calculator window and click on delay. Fill 1.25 as the threshold values (50% of Vdd = 2.5V) and keep the edges as 1 and edge types as either (in other situations you may want to make different choices here) then click OK.

delmeas

Notice the change in the calculator window. Now click on Evaluate buffer and you should get the value 8.733343432197623e-11 which is approx. 87 ps and represents tpLH for the second inverter (we measured delay from INPUT1 to INPUT2 going high). Clear Evaluate buffer and the stack and now measure tpHL for the second inverter. You need to got through the same steps except choose Edge Number 2 in the Threshold Delay dialogue box. tpHL is about 81 ps, less than tpLH as expected due to the difference in mobility between pmos and nmos. Although this may suggest that we need to increase the size of the pmos even higher we only need to do that if we are mainly interested in symmetric VTC and equal tpHL and tpLH. If we are interested in propagation delay (average of tpHL and tpLH) we may actually want to make them even less symmetric to gain speed. In order to see why we added yet another inverter we can also measure the delay from INPUT1 to OUTPUT. For this we again clear the calculator and measure the delay from INPUT1 and OUTPUT for both the first and the second edge, you should get about 171ps and 173ps. As you can see the two values are very close and also approximately equal to the previously measured tpHL + tpLH = 168ps. Basically this means that we can have just one measurement that gives us information about tp.

Let's determine now the optimal ratio a through simulation. For this we will do multiple simulations with different values for a and determine the fastest solution. Theoretically we could do those simulations manually, luckily Cadence offers the possibility of doing this automatically. Go to Tools -> Parametric Analysis in the Analog Environment window. Fill the Variable Name a with values from 1 to 3 in Linear Steps of 0.2

param

Now do Analysis -> Start in the Parametric Analysis window. The simulations will take a little longer (10 simulations are performed), be patient. Once the simulations are over we can again plot the waveforms. Go to Results -> Direct Plot -> Transient Signal and then choose INPUT1 and OUTPUT.

paramout

The first observation that we can make is that the delays are quite close which reinforces the idea that complementary static CMOS is non-ratioed. If we zoom on the HL transition you will discover that the fastest solution in this case is actually the a = 1 waveform where the pmos and nmos are equal.

paramhl

On the other hand if you look at the LH transition you can see that the solution with a = 1 has a poor rise time and a = 1.4 or a = 1.6 have much better rise times and still have small delays (compared to larger values of a). From this analysis we can conclude that a value around a = 1.6 (close to sqrt(3) = 1.73 as suggested in the book) is close to optimal for delay and decent rise time.

paramlh

It is a good idea to save your state before exiting the simulator in case you want to redo some of the simulations you can start by loading a saved state. Congratulations, this is the end of Tutorial 4. Please also read Example 3.8 in the textbook at page 137 for more discussion about the optimal ratio a.